Disk-based storage devices such as hard disk drives (HDDs) are used to provide non-volatile data storage in a wide variety of different types of data processing systems. A typical HDD comprises a spindle which holds one or more flat circular storage disks, also referred to as platters. Each storage disk comprises a substrate made from a non-magnetic material, such as aluminum or glass, which is coated with one or more thin layers of magnetic material. In operation, data is read from and written to tracks of the storage disk via a read/write head that is moved precisely across the disk surface by a positioning arm as the disk spins at high speed.
The storage capacity of HDDs continues to increase, and HDDs that can store multiple terabytes (TB) of data are currently available. However, increasing the storage capacity often involves shrinking track dimensions in order to fit more tracks onto each storage disk, such that inter-track interference (ITI) becomes an important performance issue.
A number of techniques have been developed in an attempt to further increase storage capacity. For example, a technique known as shingled magnetic recording (SMR) attempts to increase storage capacity of an HDD by “shingling” a given track over a previously written adjacent track on a storage disk. In another technique, referred to as bit-patterned media (BPM), high density tracks of magnetic islands are preformed on the surface of the storage disk, and bits of data are written to respective ones of these islands.
A conventional HDD may implement a disk locked clock (DLC) technique to reduce frequency and phase differences between an internal read channel clock and a servo timing pattern on a surface of the storage disk. This allows data sectors to be written with less frequency variation, such that a clock recovery loop in the read channel does not have to handle as much frequency variation when the data sectors are read.
A typical DLC technique may involve, for example, measuring the position and phase of servo address marks (SAMs) that provide the timing pattern on the surface of the storage disk. Additional details regarding measurement of SAMs in an HDD or other disk-based storage device may be found in U.S. Pat. No. 8,049,982, entitled “Methods and Apparatus for Measuring Servo Address Mark Distance in a Read Channel Using Selective Fine Phase Estimate,” which is commonly assigned herewith and incorporated by reference herein.
In many HDD applications it is important to calibrate the phase of an internal read channel clock relative to fixed magnetic information on the disk. For example, in the case of
BPM, the phase of the write clock must be properly aligned relative to the bit-sized magnetic islands preformed on the surface of the storage disk in order to be able to write data to these islands. A conventional write calibration procedure generally involves writing one or more test patterns on the disk using different phases or writing such test patterns with a modulated phase across a predetermined phase range, and then going back to read the test patterns to determine which phase was optimal for the desired purpose, such as determining which phase aligns most optimally with the magnetic islands in the case of BPM. As a more particular example, this write calibration procedure may involve writing a periodic test pattern to the media while ramping the write clock phase and then determining at what point during the phase ramp the best result was achieved.
In these and similar write calibration procedures, the write clock phase must be accurately controlled while the test pattern is being written. This functionality is provided by DLC circuitry of the HDD. Since the same internal read channel clock is typically used for both reading and writing, the phase of this clock will be varying during write calibration. However, the DLC circuitry still needs to lock to the SAM timing pattern on the storage disk, and without such a lock the calibration results will not be sufficiently accurate. Thus, the write calibration may be periodically interrupted in order to allow the DLC circuitry to read the timing pattern and compute an error term so as to maintain a phase lock to the timing pattern during the write clock calibration procedure. The amount of time required to perform write calibration is therefore adversely impacted by factors such as the settling time of the DLC circuitry in locking to the timing pattern as the clock phase is varied.